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| author |   Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> | 2024-10-23 12:01:36 +0300 |
|---|---|---|
| committer |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-10-26 14:00:12 +0200 |
| commit | 9174fac3b302a853b78c78f2f5ad11462b0c54b0 (patch) | |
| tree | 7118199883fc87118f531edd4e99fe32499c854f /scripts/gdb/linux/proc.py | |
| parent | clk: samsung: clk-pll: Add support for pll_{1051x,1052x} (diff) | |
| download | wireguard-linux-9174fac3b302a853b78c78f2f5ad11462b0c54b0.tar.xz wireguard-linux-9174fac3b302a853b78c78f2f5ad11462b0c54b0.zip | |
clk: samsung: Introduce Exynos8895 clock driver
CMU_TOP is the top level clock management unit which contains PLLs, muxes,
dividers and gates that feed the other clock management units.
CMU_PERIS provides clocks for GIC and MCT
CMU_FSYS0 provides clocks for USBDRD30
CMU_FSYS1 provides clocks for MMC, UFS and PCIE
CMU_PERIC0 provides clocks for UART_DBG, USI00 ~ USI03
CMU_PERIC1 provides clocks for SPI_CAM0/1, UART_BT, USI04 ~ USI13,
HSI2C_CAM0/1/2/3
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Link: https://lore.kernel.org/r/20241023090136.537395-4-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'scripts/gdb/linux/proc.py')
0 files changed, 0 insertions, 0 deletions