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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2021-06-26 09:13:37 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-12 10:52:03 +0200 |
| commit | fd8c3f6c36eb093039d4aeb20cceee00c7c6ba1a (patch) | |
| tree | 1ff9d0af260d9b8086c8106b4af4d6ceb38bf82c /scripts/gdb/linux/rbtree.py | |
| parent | clk: renesas: r9a07g044: Rename divider table (diff) | |
| download | wireguard-linux-fd8c3f6c36eb093039d4aeb20cceee00c7c6ba1a.tar.xz wireguard-linux-fd8c3f6c36eb093039d4aeb20cceee00c7c6ba1a.zip | |
clk: renesas: r9a07g044: Fix P1 Clock
As per RZ/G2L HW Manual(Rev.0.50) P1 is sourced from pll3_div2_4.
So fix the clock definitions for P1.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/rbtree.py')
0 files changed, 0 insertions, 0 deletions