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| author |   Jani Nikula <jani.nikula@intel.com> | 2017-12-21 13:08:30 +0200 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2017-12-21 13:08:31 +0200 |
| commit | 423561a0bd9d661f6121081cb0dce6972a1f0840 (patch) | |
| tree | 2f2bfc1075a79b9412fb9a3ea0ba102b85bbfeae /scripts/gdb/linux/tasks.py | |
| parent | drm/i915: Protect DDI port to DPLL map from theoretical race. (diff) | |
| parent | drm/i915/gvt: Fix pipe A enable as default for vgpu (diff) | |
| download | wireguard-linux-423561a0bd9d661f6121081cb0dce6972a1f0840.tar.xz wireguard-linux-423561a0bd9d661f6121081cb0dce6972a1f0840.zip | |
Merge tag 'gvt-fixes-2017-12-21' of https://github.com/intel/gvt-linux into drm-intel-fixes
gvt-fixes-2017-12-21:
- default pipe enable fix for virtual display (Xiaolin)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171221032500.xjofb4xyoihw3wo5@zhen-hp.sh.intel.com
Diffstat (limited to 'scripts/gdb/linux/tasks.py')
0 files changed, 0 insertions, 0 deletions