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| author |   Philipp Zabel <p.zabel@pengutronix.de> | 2017-10-09 12:03:31 +0200 |
|---|---|---|
| committer |   Lucas Stach <l.stach@pengutronix.de> | 2017-10-10 12:10:20 +0200 |
| commit | 8272170f7da34e2554bed10ab76582094ea6816d (patch) | |
| tree | 480b492ea5bd1668fead9d998b7db1e6d19010d9 /scripts/gdb/linux/tasks.py | |
| parent | drm/etnaviv: reduce reset delay (diff) | |
| download | wireguard-linux-8272170f7da34e2554bed10ab76582094ea6816d.tar.xz wireguard-linux-8272170f7da34e2554bed10ab76582094ea6816d.zip | |
drm/etnaviv: remove unnecessary clock stabilization delay
There is no reason to wait for clock stabilization here, as the clock
framework guarantees that PLL clock sources are stable before clk_enable
returns.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'scripts/gdb/linux/tasks.py')
0 files changed, 0 insertions, 0 deletions