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author | 2017-12-11 22:51:35 +0000 | |
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committer | 2017-12-12 19:11:26 +0100 | |
commit | a03fe72572c12e98f4173f8a535f32468e48b6ec (patch) | |
tree | 2361d979b2baec7d3bb0e05273ae7e065f71ad82 /scripts/gdb/linux/tasks.py | |
parent | MIPS: CPS: Fix r1 .set mt assembler warning (diff) | |
download | wireguard-linux-a03fe72572c12e98f4173f8a535f32468e48b6ec.tar.xz wireguard-linux-a03fe72572c12e98f4173f8a535f32468e48b6ec.zip |
MIPS: Factor out NT_PRFPREG regset access helpers
In preparation to fix a commit 72b22bbad1e7 ("MIPS: Don't assume 64-bit
FP registers for FP regset") FCSR access regression factor out
NT_PRFPREG regset access helpers for the non-MSA and the MSA variants
respectively, to avoid having to deal with excessive indentation in the
actual fix.
No functional change, however use `target->thread.fpu.fpr[0]' rather
than `target->thread.fpu.fpr[i]' for FGR holding type size determination
as there's no `i' variable to refer to anymore, and for the factored out
`i' variable declaration use `unsigned int' rather than `unsigned' as
its type, following the common style.
Signed-off-by: Maciej W. Rozycki <macro@mips.com>
Fixes: 72b22bbad1e7 ("MIPS: Don't assume 64-bit FP registers for FP regset")
Cc: James Hogan <james.hogan@mips.com>
Cc: Paul Burton <Paul.Burton@mips.com>
Cc: Alex Smith <alex@alex-smith.me.uk>
Cc: Dave Martin <Dave.Martin@arm.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: stable@vger.kernel.org # v3.15+
Patchwork: https://patchwork.linux-mips.org/patch/17925/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'scripts/gdb/linux/tasks.py')
0 files changed, 0 insertions, 0 deletions