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| author | 2019-12-19 14:44:59 +0800 | |
|---|---|---|
| committer | 2019-12-20 03:32:24 -0800 | |
| commit | d411cf02ed0260dacc4b2fd61dd5040fc2aa97e7 (patch) | |
| tree | d98782836429105d82651dcf854cbb42799a1132 /scripts/gdb/linux/tasks.py | |
| parent | riscv: Fix use of undefined config option CONFIG_CONFIG_MMU (diff) | |
| download | wireguard-linux-d411cf02ed0260dacc4b2fd61dd5040fc2aa97e7.tar.xz wireguard-linux-d411cf02ed0260dacc4b2fd61dd5040fc2aa97e7.zip | |
riscv: fix scratch register clearing in M-mode.
This patch fixes that the sscratch register clearing in M-mode. It cleared
sscratch register in M-mode, but it should clear mscratch register. That will
cause kernel trap if the CPU core doesn't support S-mode when trying to access
sscratch.
Fixes: 9e80635619b5 ("riscv: clear the instruction cache and all registers when booting")
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'scripts/gdb/linux/tasks.py')
0 files changed, 0 insertions, 0 deletions
