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| author |   Aya Levin <ayal@nvidia.com> | 2021-04-11 09:33:12 +0300 |
|---|---|---|
| committer |   Saeed Mahameed <saeedm@nvidia.com> | 2021-04-14 16:12:57 -0700 |
| commit | 7a320c9db3e73fb6c4f9a331087df9df18767221 (patch) | |
| tree | e6d97004dd8e7f304b403c57b760b457fb976799 /scripts/gdb/linux/timerlist.py | |
| parent | net/mlx5: Fix setting of devlink traps in switchdev mode (diff) | |
| download | wireguard-linux-7a320c9db3e73fb6c4f9a331087df9df18767221.tar.xz wireguard-linux-7a320c9db3e73fb6c4f9a331087df9df18767221.zip | |
net/mlx5e: Fix setting of RS FEC mode
Change register setting from bit number to bit mask.
Fixes: b5ede32d3329 ("net/mlx5e: Add support for FEC modes based on 50G per lane links")
Signed-off-by: Aya Levin <ayal@nvidia.com>
Reviewed-by: Eran Ben Elisha <eranbe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'scripts/gdb/linux/timerlist.py')
0 files changed, 0 insertions, 0 deletions