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| author |   Xianwei Zhao <xianwei.zhao@amlogic.com> | 2024-05-22 16:27:23 +0800 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2024-06-04 10:27:23 +0200 |
| commit | 0e6be855a96dd44effce97b6b8d0cf0d0d0b7303 (patch) | |
| tree | 12f83c416bab4ea3be0bd835e90f91591b4c321a /scripts/gdb/linux/utils.py | |
| parent | dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format (diff) | |
| download | wireguard-linux-0e6be855a96dd44effce97b6b8d0cf0d0d0b7303.tar.xz wireguard-linux-0e6be855a96dd44effce97b6b8d0cf0d0d0b7303.zip | |
dt-bindings: clock: add Amlogic C3 PLL clock controller
Add the PLL clock controller dt-bindings for Amlogic C3 SoC family.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240522082727.3029656-2-xianwei.zhao@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions