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| author |   Ben Skeggs <bskeggs@redhat.com> | 2019-05-10 11:57:04 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2019-05-14 16:58:06 +1000 |
| commit | 13d03e9daf70dab032c03dc172e75bb98ad899c4 (patch) | |
| tree | ea35f753043200870bd8a1b5065d737e7020bb41 /scripts/gdb/linux/utils.py | |
| parent | drm/nouveau/core: initial support for boards with TU117 chipset (diff) | |
| download | wireguard-linux-13d03e9daf70dab032c03dc172e75bb98ad899c4.tar.xz wireguard-linux-13d03e9daf70dab032c03dc172e75bb98ad899c4.zip | |
drm/nouveau/disp/dp: respect sink limits when selecting failsafe link configuration
Where possible, we want the failsafe link configuration (one which won't
hang the OR during modeset because of not enough bandwidth for the mode)
to also be supported by the sink.
This prevents "link rate unsupported by sink" messages when link training
fails.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions