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| author |   Richard Zhu <hongxing.zhu@nxp.com> | 2021-12-24 10:28:05 +0800 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2021-12-26 12:13:32 +0000 |
| commit | 178e244cb6e209971b0ded9977e5146b73fe1f45 (patch) | |
| tree | afb9584917d3bd2413e02b2132947ceffd9947c6 /scripts/gdb/linux/utils.py | |
| parent | dt-bindings: imx6q-pcie: Add PHY phandles and name properties (diff) | |
| download | wireguard-linux-178e244cb6e209971b0ded9977e5146b73fe1f45.tar.xz wireguard-linux-178e244cb6e209971b0ded9977e5146b73fe1f45.zip | |
PCI: imx: Add the imx8mm pcie support
i.MX8MM PCIe works mostly like the i.MX8MQ one, but has a different PHY
and allows to output the internal PHY reference clock via the refclk pad.
Add the i.MX8MM PCIe support based on the standalone PHY driver.
Link: https://lore.kernel.org/r/1640312885-31142-2-git-send-email-hongxing.zhu@nxp.com
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions