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| author |   Andrew Jeffery <andrew@aj.id.au> | 2021-05-20 11:43:34 +0930 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-05-20 17:14:50 +0200 |
| commit | 1f06f5713f5278b7768031150ceb43d1127b9ad6 (patch) | |
| tree | 68b69b412ad19b587125d3dd99beec885ece1af7 /scripts/gdb/linux/utils.py | |
| parent | serial: 8250: Add UART_BUG_TXRACE workaround for Aspeed VUART (diff) | |
| download | wireguard-linux-1f06f5713f5278b7768031150ceb43d1127b9ad6.tar.xz wireguard-linux-1f06f5713f5278b7768031150ceb43d1127b9ad6.zip | |
serial: 8250: Use BIT(x) for UART_{CAP,BUG}_*
BIT(x) improves readability and safety with respect to shifts.
Reviewed-by: Jiri Slaby <jirislaby@kernel.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20210520021334.497341-3-andrew@aj.id.au
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions