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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2022-01-13 09:57:51 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2022-01-13 09:57:51 -0600 |
| commit | 2709f0338d4c8cb17e11b448f0257afefae57475 (patch) | |
| tree | 1892d2fb65213593d70b6d54a2bacb521dd61739 /scripts/gdb/linux/utils.py | |
| parent | Merge branch 'remotes/lorenzo/pci/xilinx-nwl' (diff) | |
| parent | PCI: pci-bridge-emul: Set PCI_STATUS_CAP_LIST for PCIe device (diff) | |
| download | wireguard-linux-2709f0338d4c8cb17e11b448f0257afefae57475.tar.xz wireguard-linux-2709f0338d4c8cb17e11b448f0257afefae57475.zip | |
Merge branch 'remotes/lorenzo/pci/bridge-emul'
- Make emulated ROM BAR read-only by default (Pali Rohár)
- Make some emulated legacy PCI bits read-only for PCIe devices (Pali
Rohár)
- Update reserved bits in emulated PCIe Capability (Pali Rohár)
- Allow drivers to emulate different PCIe Capability versions (Pali Rohár)
- Set emulated Capabilities List bit for all PCIe devices, since they must
have at least a PCIe Capability (Pali Rohár)
* remotes/lorenzo/pci/bridge-emul:
PCI: pci-bridge-emul: Set PCI_STATUS_CAP_LIST for PCIe device
PCI: pci-bridge-emul: Correctly set PCIe capabilities
PCI: pci-bridge-emul: Fix definitions of reserved bits
PCI: pci-bridge-emul: Properly mark reserved PCIe bits in PCI config space
PCI: pci-bridge-emul: Make expansion ROM Base Address register read-only
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions