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| author |   Neil Armstrong <narmstrong@baylibre.com> | 2019-08-26 09:25:37 +0200 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2019-08-26 11:04:42 +0200 |
| commit | 2edccd319fdef9bc35c06fe4150b21099ac99579 (patch) | |
| tree | 0779a793486bd173ebdc03ce7cd5d92d48c888b2 /scripts/gdb/linux/utils.py | |
| parent | clk: meson: g12a: add support for SM1 GP1 PLL (diff) | |
| download | wireguard-linux-2edccd319fdef9bc35c06fe4150b21099ac99579.tar.xz wireguard-linux-2edccd319fdef9bc35c06fe4150b21099ac99579.zip | |
clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
The Amlogic SM1 DynamIQ Shared Unit has a dedicated clock tree similar to
the CPU clock tree with a supplementaty mux to select the CPU0 clock
instead.
Leave this as read-only since it's set up by the early boot stages.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions