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| author |   Dmitry Rokosov <ddrokosov@salutedevices.com> | 2024-05-15 21:47:27 +0300 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2024-06-10 12:16:45 +0200 |
| commit | 41056416ed538d1a05dbba57060c02acdc5154e7 (patch) | |
| tree | 63c029941df8270190a8a4e64e544d18635e9cc3 /scripts/gdb/linux/utils.py | |
| parent | dt-bindings: clock: meson: a1: pll: introduce new syspll bindings (diff) | |
| download | wireguard-linux-41056416ed538d1a05dbba57060c02acdc5154e7.tar.xz wireguard-linux-41056416ed538d1a05dbba57060c02acdc5154e7.zip | |
dt-bindings: clock: meson: a1: peripherals: support sys_pll input
The 'sys_pll' input is an optional clock that can be used to generate
'sys_pll_div16', which serves as one of the sources for the GEN clock.
Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240515185103.20256-5-ddrokosov@salutedevices.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions