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| author |   Yash Shah <yash.shah@sifive.com> | 2019-05-06 16:18:39 +0530 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@sifive.com> | 2019-05-16 20:42:13 -0700 |
| commit | 5545b6d1ba25ce4a3a339b1edb760e666e693599 (patch) | |
| tree | f0578abef4b66e0aaf6ffcf087df6a2a3643183b /scripts/gdb/linux/utils.py | |
| parent | RISC-V: Avoid using invalid intermediate translations (diff) | |
| download | wireguard-linux-5545b6d1ba25ce4a3a339b1edb760e666e693599.tar.xz wireguard-linux-5545b6d1ba25ce4a3a339b1edb760e666e693599.zip | |
RISC-V: Add DT documentation for SiFive L2 Cache Controller
Add device tree bindings for SiFive FU540 L2 cache controller driver
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions