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author | 2022-05-26 20:13:02 +0800 | |
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committer | 2022-05-26 14:43:26 +0100 | |
commit | 5fa66f29937eb806997a4d1d3edd360ef4e93db9 (patch) | |
tree | cec315153a7acd24c41257bdbc469ba3e7e55ba5 /scripts/gdb/linux/utils.py | |
parent | ASoC: rt5640: Do not manipulate pin "Platform Clock" if the "Platform Clock" is not in the DAPM (diff) | |
download | wireguard-linux-5fa66f29937eb806997a4d1d3edd360ef4e93db9.tar.xz wireguard-linux-5fa66f29937eb806997a4d1d3edd360ef4e93db9.zip |
ASoC: Intel: common: fix typo for tplg naming
Correct typo form sof-adl-mx98360a-nau8825.tplg to
sof-adl-max98360a-nau8825.tplg. The reason is tplg naming without naming
limitaion of length. It will be consistency with sof topology generation.
Signed-off-by: David Lin <CTLIN0@nuvoton.com>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220526121301.1819541-1-CTLIN0@nuvoton.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions