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| author |   Marc Zyngier <marc.zyngier@arm.com> | 2019-09-13 10:57:50 +0100 |
|---|---|---|
| committer |   Will Deacon <will@kernel.org> | 2019-10-08 12:25:25 +0100 |
| commit | 603afdc9438ac546181e843f807253d75d3dbc45 (patch) | |
| tree | 3b6e284befb8384f0babee6d8afff2f6da9cb191 /scripts/gdb/linux/utils.py | |
| parent | arm64: Avoid Cavium TX2 erratum 219 when switching TTBR (diff) | |
| download | wireguard-linux-603afdc9438ac546181e843f807253d75d3dbc45.tar.xz wireguard-linux-603afdc9438ac546181e843f807253d75d3dbc45.zip | |
arm64: Allow CAVIUM_TX2_ERRATUM_219 to be selected
Allow the user to select the workaround for TX2-219, and update
the silicon-errata.rst file to reflect this.
Cc: <stable@vger.kernel.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions