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| author |   Icenowy Zheng <icenowy@aosc.io> | 2019-07-28 11:12:23 +0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@bootlin.com> | 2019-08-12 10:05:13 +0200 |
| commit | 720099603d1f62e37b789366d7e89824b009ca28 (patch) | |
| tree | 0ce62e9c102efc106c55f594391a29c368f57acc /scripts/gdb/linux/utils.py | |
| parent | dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU (diff) | |
| download | wireguard-linux-720099603d1f62e37b789366d7e89824b009ca28.tar.xz wireguard-linux-720099603d1f62e37b789366d7e89824b009ca28.zip | |
clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
The MMC2 clock slices are currently not defined in V3s CCU driver, which
makes MMC2 not working.
Fix this issue.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions