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| author |   Max Filippov <jcmvbkbc@gmail.com> | 2019-10-15 21:51:43 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2019-10-16 00:14:33 -0700 |
| commit | 775fd6bfefc66a8c33e91dd9687ed530643b954d (patch) | |
| tree | 847cb936bf566b68a73869c5b505f5618e60fc65 /scripts/gdb/linux/utils.py | |
| parent | xtensa: virt: fix PCI IO ports mapping (diff) | |
| download | wireguard-linux-775fd6bfefc66a8c33e91dd9687ed530643b954d.tar.xz wireguard-linux-775fd6bfefc66a8c33e91dd9687ed530643b954d.zip | |
xtensa: fix change_bit in exclusive access option
change_bit implementation for XCHAL_HAVE_EXCLUSIVE case changes all bits
except the one required due to copy-paste error from clear_bit.
Cc: stable@vger.kernel.org # v5.2+
Fixes: f7c34874f04a ("xtensa: add exclusive atomics support")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions