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author | 2019-08-14 09:45:43 -0700 | |
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committer | 2019-08-14 09:45:43 -0700 | |
commit | 7c9dc000bd199f1f90c4e9f1b2814c0dd0ebaa2c (patch) | |
tree | c54802e76532ea7e4d3a48f6f1a7a35f5f8975f8 /scripts/gdb/linux/utils.py | |
parent | Linus 5.3-rc1 (diff) | |
parent | Merge branch 'v5.4/dt' into v5.4/drivers (diff) | |
download | wireguard-linux-7c9dc000bd199f1f90c4e9f1b2814c0dd0ebaa2c.tar.xz wireguard-linux-7c9dc000bd199f1f90c4e9f1b2814c0dd0ebaa2c.zip |
Merge tag 'clk-meson-v5.4-1' of https://github.com/BayLibre/clk-meson into clk-meson
Pull Amlogic clock changes from Jerome Brunet:
- Migrate to new clock description method
- Add DVFS support to g12
* tag 'clk-meson-v5.4-1' of https://github.com/BayLibre/clk-meson:
clk: meson: g12a: expose CPUB clock ID for G12B
clk: meson: g12a: add notifiers to handle cpu clock change
clk: meson: add g12a cpu dynamic divider driver
clk: core: introduce clk_hw_set_parent()
clk: meson: remove clk input helper
clk: meson: remove ee input bypass clocks
clk: meson: clk-regmap: migrate to new parent description method
clk: meson: meson8b: migrate to the new parent description method
clk: meson: axg: migrate to the new parent description method
clk: meson: gxbb: migrate to the new parent description method
clk: meson: g12a: migrate to the new parent description method
clk: meson: remove ao input bypass clocks
clk: meson: axg-aoclk: migrate to the new parent description method
clk: meson: gxbb-aoclk: migrate to the new parent description method
clk: meson: g12a-aoclk: migrate to the new parent description method
clk: meson: axg-audio: migrate to the new parent description method
clk: meson: g12a: fix hifi typo in mali parent_names
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions