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| author |   Christian Marangi <ansuelsmth@gmail.com> | 2024-06-28 12:55:41 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2024-07-08 12:01:46 -0700 |
| commit | 9f7809c6a8824b7147595b3c36e633ffc81fe2ab (patch) | |
| tree | 8b39db606fd6585c04ca0e6d0393c02ae2e41938 /scripts/gdb/linux/utils.py | |
| parent | clk: mediatek: Add a module description where missing (diff) | |
| download | wireguard-linux-9f7809c6a8824b7147595b3c36e633ffc81fe2ab.tar.xz wireguard-linux-9f7809c6a8824b7147595b3c36e633ffc81fe2ab.zip | |
dt-bindings: clock: mediatek: add syscon compatible for mt7622 pciesys
Add required syscon compatible for mt7622 pciesys. This is required for
SATA interface as the regs are shared.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20240628105542.5456-2-ansuelsmth@gmail.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions