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| author |   Chun-Jie Chen <chun-jie.chen@mediatek.com> | 2021-07-26 18:57:16 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2021-07-27 10:53:09 -0700 |
| commit | a1a5b6b0a840dbcd4baa0e775489a52d1e9c2156 (patch) | |
| tree | b26d36264f6f73fce9acd85bdcfcf1f0f7ec381e /scripts/gdb/linux/utils.py | |
| parent | clk: mediatek: Add MT8192 mmsys clock support (diff) | |
| download | wireguard-linux-a1a5b6b0a840dbcd4baa0e775489a52d1e9c2156.tar.xz wireguard-linux-a1a5b6b0a840dbcd4baa0e775489a52d1e9c2156.zip | |
clk: mediatek: Add MT8192 msdc clock support
Add MT8192 msdc and msdc top clock providers
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-19-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions