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| author |   Robin Gong <yibin.gong@nxp.com> | 2019-06-25 17:43:22 +0800 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2019-07-03 13:28:23 +0530 |
| commit | a7c5c6f6bc295d6c158db4ef9d1ca6770032669d (patch) | |
| tree | 8318592ae6e18900db8d777d94f37662b81027e1 /scripts/gdb/linux/utils.py | |
| parent | dmaengine: fsl-edma-common: version check for v2 instead (diff) | |
| download | wireguard-linux-a7c5c6f6bc295d6c158db4ef9d1ca6770032669d.tar.xz wireguard-linux-a7c5c6f6bc295d6c158db4ef9d1ca6770032669d.zip | |
dt-bindings: dma: fsl-edma: add new i.mx7ulp-edma
More channel interrupts, one more clock, and only one
dmamux on i.mx7ulp-edma.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Tested-by: Angelo Dureghello <angelo@sysam.it>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions