diff options
| author |   Vladimir Kondratiev <vladimir.kondratiev@linux.intel.com> | 2019-07-16 10:36:56 +0300 |
|---|---|---|
| committer |   Paul Burton <paul.burton@mips.com> | 2019-07-18 14:41:04 -0700 |
| commit | b8bea8a5e5d942e62203416ab41edecaed4fda02 (patch) | |
| tree | 06bd6eedc7a4d500436542a7f0943be2762d3c14 /scripts/gdb/linux/utils.py | |
| parent | MIPS: kernel: only use i8253 clocksource with periodic clockevent (diff) | |
| download | wireguard-linux-b8bea8a5e5d942e62203416ab41edecaed4fda02.tar.xz wireguard-linux-b8bea8a5e5d942e62203416ab41edecaed4fda02.zip | |
mips: fix cacheinfo
Because CONFIG_OF defined for MIPS, cacheinfo attempts to fill information
from DT, ignoring data filled by architecture routine. This leads to error
reported
cacheinfo: Unable to detect cache hierarchy for CPU 0
Way to fix this provided in
commit fac51482577d ("drivers: base: cacheinfo: fix x86 with
CONFIG_OF enabled")
Utilize same mechanism to report that cacheinfo set by architecture
specific function
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@linux.intel.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions