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author | 2019-06-24 20:07:46 -0700 | |
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committer | 2019-06-24 20:07:46 -0700 | |
commit | c0bc660c906821acfbfde9dbdea15e6d843d982a (patch) | |
tree | 29ae0e063358fbc41ea8d035c8c4a5a668ee32c8 /scripts/gdb/linux/utils.py | |
parent | Linux 5.2-rc1 (diff) | |
parent | clk: samsung: Add bus clock for GPU/G3D on Exynos4412 (diff) | |
download | wireguard-linux-c0bc660c906821acfbfde9dbdea15e6d843d982a.tar.xz wireguard-linux-c0bc660c906821acfbfde9dbdea15e6d843d982a.zip |
Merge tag 'clk-v5.3-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki:
- Addition of clocks required for new Exynos5422 Dynamic Memory
Controller driver
- clock definition for Exynos4412 Mali
- minor clean up of clk-exynos5433.c
* tag 'clk-v5.3-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: Add bus clock for GPU/G3D on Exynos4412
clk: samsung: add new clocks for DMC for Exynos5422 SoC
clk: samsung: add BPLL rate table for Exynos 5422 SoC
clk: samsung: add needed IDs for DMC clocks in Exynos5420
clk: samsung: exynos5433: Use of_clk_get_parent_count()
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions