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| author |   Manikanta Maddireddy <mmaddireddy@nvidia.com> | 2019-06-18 23:31:58 +0530 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2019-06-20 17:40:48 +0100 |
| commit | c894121d014260af3fd199e1d2a56d4af5ff8ba9 (patch) | |
| tree | 12bd14e4e0410cc18b9ddfeafcddbe58a400718c /scripts/gdb/linux/utils.py | |
| parent | PCI: tegra: Program AFI_CACHE_BAR_{0,1}_{ST,SZ} registers only for Tegra20 (diff) | |
| download | wireguard-linux-c894121d014260af3fd199e1d2a56d4af5ff8ba9.tar.xz wireguard-linux-c894121d014260af3fd199e1d2a56d4af5ff8ba9.zip | |
PCI: tegra: Change PRSNT_SENSE IRQ log to debug
PRSNT_MAP bit field is programmed to update the slot present status.
PRSNT_SENSE IRQ is triggered when this bit field is programmed, which is
not an error. Add a new if condition to trap PRSNT_SENSE code and print
it with debug log level.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions