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| author |   Miquel Raynal <miquel.raynal@bootlin.com> | 2019-07-31 14:21:23 +0200 |
|---|---|---|
| committer |   Gregory CLEMENT <gregory.clement@bootlin.com> | 2019-08-27 16:17:28 +0200 |
| commit | d04abe999e20a57c96b305d329e480ffe057c9ec (patch) | |
| tree | 35aa9000d6947ef71bd98f524ff2f6c1266d8cb3 /scripts/gdb/linux/utils.py | |
| parent | arm64: dts: marvell: Add CP110 COMPHY clocks (diff) | |
| download | wireguard-linux-d04abe999e20a57c96b305d329e480ffe057c9ec.tar.xz wireguard-linux-d04abe999e20a57c96b305d329e480ffe057c9ec.zip | |
arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k
based boards.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions