diff options
| author |   Kan Liang <kan.liang@linux.intel.com> | 2019-10-08 08:50:07 -0700 |
|---|---|---|
| committer |   Ingo Molnar <mingo@kernel.org> | 2019-10-12 15:13:09 +0200 |
| commit | f1857a2467755e5faa3c727d7146b6db960abee1 (patch) | |
| tree | c50d4c97d82f3c944cf70ce96d3453f090da0596 /scripts/gdb/linux/utils.py | |
| parent | perf/x86/msr: Add new CPU model numbers for Ice Lake (diff) | |
| download | wireguard-linux-f1857a2467755e5faa3c727d7146b6db960abee1.tar.xz wireguard-linux-f1857a2467755e5faa3c727d7146b6db960abee1.zip | |
perf/x86/cstate: Update C-state counters for Ice Lake
There is no Core C3 C-State counter for Ice Lake.
Package C8/C9/C10 C-State counters are added for Ice Lake.
Introduce a new event list, icl_cstates, for Ice Lake.
Update the comments accordingly.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Fixes: f08c47d1f86c ("perf/x86/intel/cstate: Add Icelake support")
Link: https://lkml.kernel.org/r/1570549810-25049-7-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions