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| author |   Max Filippov <jcmvbkbc@gmail.com> | 2022-04-18 00:14:00 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2022-05-01 19:51:23 -0700 |
| commit | f29cab2906346fa93831376256e01f5a6629f979 (patch) | |
| tree | 07ee91a5f30628a3cbdb349d881874b1ed116e5e /scripts/gdb/linux/utils.py | |
| parent | xtensa: merge SAVE_CP_REGS_TAB and LOAD_CP_REGS_TAB (diff) | |
| download | wireguard-linux-f29cab2906346fa93831376256e01f5a6629f979.tar.xz wireguard-linux-f29cab2906346fa93831376256e01f5a6629f979.zip | |
xtensa: get rid of stack frame in coprocessor_flush
coprocessor_flush is an ordinary function, it can use all registers.
Don't reserve stack frame for it and use a7 to preserve a0 around the
context saving call.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions