diff options
| author |   Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2024-02-25 16:13:34 +0100 |
|---|---|---|
| committer |   Daniel Lezcano <daniel.lezcano@linaro.org> | 2024-02-26 10:07:25 +0100 |
| commit | f31c204850f9d93906b5ac8c203b2066524ff245 (patch) | |
| tree | acce72ea6e25490adfc043296349abefa6e83029 /scripts/gdb/linux/utils.py | |
| parent | dt-bindings: timer: add Ralink SoCs system tick counter (diff) | |
| download | wireguard-linux-f31c204850f9d93906b5ac8c203b2066524ff245.tar.xz wireguard-linux-f31c204850f9d93906b5ac8c203b2066524ff245.zip | |
clocksource/drivers/arm_global_timer: Make gt_target_rate unsigned long
Change the data type of gt_target_rate to unsigned long as this is what
we get back from clk_get_rate().
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20240225151336.2728533-2-martin.blumenstingl@googlemail.com
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions