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| author |   Peng Fan <peng.fan@nxp.com> | 2019-08-14 09:53:12 +0800 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2019-08-19 13:57:47 +0200 |
| commit | f8cade831018d80eaa3d9f64dac5a52d8715de55 (patch) | |
| tree | 6080ddf070dbdeaff05d124b56cc41f89b12645b /scripts/gdb/linux/utils.py | |
| parent | clk: imx8mn: Add GIC clock (diff) | |
| download | wireguard-linux-f8cade831018d80eaa3d9f64dac5a52d8715de55.tar.xz wireguard-linux-f8cade831018d80eaa3d9f64dac5a52d8715de55.zip | |
clk: imx8mn: fix int pll clk gate
To Frac pll, the gate shift is 13, however to Int PLL the gate shift
is 11.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions