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| author |   Chris Morgan <macromorgan@hotmail.com> | 2024-06-05 12:20:47 -0500 |
|---|---|---|
| committer |   Chen-Yu Tsai <wens@csie.org> | 2024-06-22 20:09:20 +0800 |
| commit | 002cf0dfa201e44685e3b96ae06b8de258b8b2c2 (patch) | |
| tree | 21b72ee28536f614b7738ff2cd5e4f955e53e1a8 /scripts/generate_rust_analyzer.py | |
| parent | Merge branch 'sunxi/shared-clk-ids-for-6.11' into sunxi/clk-for-6.11 (diff) | |
| download | wireguard-linux-002cf0dfa201e44685e3b96ae06b8de258b8b2c2.tar.xz wireguard-linux-002cf0dfa201e44685e3b96ae06b8de258b8b2c2.zip | |
clk: sunxi-ng: h616: Add clock/reset for GPADC
Add the GPADC required clock and reset which is used for the onboard
GPADC.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20240605172049.231108-3-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions