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author | 2022-08-26 11:26:27 -0700 | |
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committer | 2022-08-26 11:26:27 -0700 | |
commit | 012bd7e859df9d6aa0a8ab4484c00aeded108071 (patch) | |
tree | 830820ba3d8a903d91968da410f012331125a2fd /scripts/generate_rust_analyzer.py | |
parent | Merge tag 'loongarch-fixes-6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson (diff) | |
parent | Merge branch 'riscv-variable_fixes_without_kvm' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git into fixes (diff) | |
download | wireguard-linux-012bd7e859df9d6aa0a8ab4484c00aeded108071.tar.xz wireguard-linux-012bd7e859df9d6aa0a8ab4484c00aeded108071.zip |
Merge tag 'riscv-for-linus-6.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Palmer Dabbelt:
- A handful of fixes for the Microchip device trees
- A pair of fixes to eliminate build warnings
* tag 'riscv-for-linus-6.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: dts: microchip: mpfs: remove pci axi address translation property
riscv: dts: microchip: mpfs: remove bogus card-detect-delay
riscv: dts: microchip: mpfs: remove ti,fifo-depth property
riscv: dts: microchip: mpfs: fix incorrect pcie child node name
riscv: traps: add missing prototype
riscv: signal: fix missing prototype warning
riscv: dts: microchip: correct L2 cache interrupts
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
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