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| author |   Jani Nikula <jani.nikula@intel.com> | 2023-04-06 16:46:14 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2023-04-24 22:40:40 +0300 |
| commit | 13525645e2246ebc8a21bd656248d86022a6ee8f (patch) | |
| tree | b58f43a113d5b2996d570c931e5883b7c5ab7e60 /scripts/generate_rust_analyzer.py | |
| parent | firmware/sysfb: Fix VESA format selection (diff) | |
| download | wireguard-linux-13525645e2246ebc8a21bd656248d86022a6ee8f.tar.xz wireguard-linux-13525645e2246ebc8a21bd656248d86022a6ee8f.zip | |
drm/dsc: fix drm_edp_dsc_sink_output_bpp() DPCD high byte usage
The operator precedence between << and & is wrong, leading to the high
byte being completely ignored. For example, with the 6.4 format, 32
becomes 0 and 24 becomes 8. Fix it, and remove the slightly confusing
and unnecessary DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT macro while at it.
Fixes: 0575650077ea ("drm/dp: DRM DP helper/macros to get DP sink DSC parameters")
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Manasi Navare <navaremanasi@google.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: <stable@vger.kernel.org> # v5.0+
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230406134615.1422509-1-jani.nikula@intel.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions