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| author |   Andrew Jones <ajones@ventanamicro.com> | 2022-10-02 10:18:54 +0530 |
|---|---|---|
| committer |   Anup Patel <anup@brainfault.org> | 2022-10-02 10:18:54 +0530 |
| commit | 1b5cbb8733f924c99bc48a8e4c2a95449f0f514d (patch) | |
| tree | 70f6016867035f1ee9224f75e7a3c1d164230165 /scripts/generate_rust_analyzer.py | |
| parent | RISC-V: KVM: Allow Guest use Zihintpause extension (diff) | |
| download | wireguard-linux-1b5cbb8733f924c99bc48a8e4c2a95449f0f514d.tar.xz wireguard-linux-1b5cbb8733f924c99bc48a8e4c2a95449f0f514d.zip | |
RISC-V: KVM: Make ISA ext mappings explicit
While adding new extensions at the bottom of the array isn't hard to
do, it's a pain to review in order to ensure we're not missing any.
Also, resolving merge conflicts for multiple new ISA extensions can be
error-prone. To make adding new mappings foolproof, explicitly assign
the array elements. And, now that the order doesn't matter, we can
alphabetize the extensions, so we do that too.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions