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| author |   Peter Ujfalusi <peter.ujfalusi@linux.intel.com> | 2022-06-30 09:56:37 +0300 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2022-07-07 17:16:39 +0100 |
| commit | 219af251bd1694bce1f627d238347d2eaf13de61 (patch) | |
| tree | 8a1a619d524794ceeaddfdeb08e370ae04a20b73 /scripts/generate_rust_analyzer.py | |
| parent | ASoC: rt5640: Fix the wrong state of JD1 and JD2 (diff) | |
| download | wireguard-linux-219af251bd1694bce1f627d238347d2eaf13de61.tar.xz wireguard-linux-219af251bd1694bce1f627d238347d2eaf13de61.zip | |
ASoC: Intel: Skylake: Correct the ssp rate discovery in skl_get_ssp_clks()
The present flag is only set once when one rate has been found to be saved.
This will effectively going to ignore any rate discovered at later time and
based on the code, this is not the intention.
Fixes: bc2bd45b1f7f3 ("ASoC: Intel: Skylake: Parse nhlt and register clock device")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20220630065638.11183-2-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions