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| author |   Siddharth Vadapalli <s-vadapalli@ti.com> | 2024-11-04 13:14:20 +0530 |
|---|---|---|
| committer |   Krzysztof Wilczyński <kwilczynski@kernel.org> | 2024-11-04 12:43:36 +0000 |
| commit | 22a9120479a40a56c13c5e473a0100fad2e017c0 (patch) | |
| tree | e2b08ffd3dd7c131705b4a543574f130224501fb /scripts/generate_rust_analyzer.py | |
| parent | PCI: j721e: Add PCIe support for J722S SoC (diff) | |
| download | wireguard-linux-22a9120479a40a56c13c5e473a0100fad2e017c0.tar.xz wireguard-linux-22a9120479a40a56c13c5e473a0100fad2e017c0.zip | |
PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds
According to Section 2.2 of the PCI Express Card Electromechanical
Specification (Revision 5.1), in order to ensure that the power and the
reference clock are stable, PERST# has to be deasserted after a delay of
100 milliseconds (TPVPERL).
Currently, it is being assumed that the power is already stable, which
is not necessarily true.
Hence, change the delay to PCIE_T_PVPERL_MS to guarantee that power and
reference clock are stable.
Fixes: f3e25911a430 ("PCI: j721e: Add TI J721E PCIe driver")
Fixes: f96b69713733 ("PCI: j721e: Use T_PERST_CLK_US macro")
Link: https://lore.kernel.org/r/20241104074420.1862932-1-s-vadapalli@ti.com
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions