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| author |   Peichen Huang <PeiChen.Huang@amd.com> | 2024-12-25 15:51:34 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2025-01-10 12:12:29 -0500 |
| commit | 230dced3e2b712017c03ce0afb3f8c48d8af20ee (patch) | |
| tree | 9a302cbd7dd3cde788e742d2ce0ddecaa9d156bb /scripts/generate_rust_analyzer.py | |
| parent | drm/amd/display: Apply DML21 Patches (diff) | |
| download | wireguard-linux-230dced3e2b712017c03ce0afb3f8c48d8af20ee.tar.xz wireguard-linux-230dced3e2b712017c03ce0afb3f8c48d8af20ee.zip | |
drm/amd/display: improve dpia pre-train
[WHY]
We see unstable DP LL 4.2.1.3 test result with dpia pre-train. It is
because the outbox interrupt mechanism can not handle HPD
immediately and require some improvement.
[HOW]
1. not enable link if hpd_pending is true.
2. abort pre-train if training failed and hpd_pending is true.
3. check if 2 lane supported when it is alt mode
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Peichen Huang <PeiChen.Huang@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions