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| author |   Atish Patra <atish.patra@wdc.com> | 2022-02-18 16:46:59 -0800 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-03-21 15:01:33 -0700 |
| commit | 23b1f18326ec3f6966ac8851b20b6d3d22380520 (patch) | |
| tree | a83c4bea1242deae4bbda3c6eb5edd2bde6a420f /scripts/generate_rust_analyzer.py | |
| parent | RISC-V: Add sscofpmf extension support (diff) | |
| download | wireguard-linux-23b1f18326ec3f6966ac8851b20b6d3d22380520.tar.xz wireguard-linux-23b1f18326ec3f6966ac8851b20b6d3d22380520.zip | |
Documentation: riscv: Remove the old documentation
The existing pmu documentation describes the limitation of perf
infrastructure in RISC-V ISA and limited feature set of perf in RISC-V.
However, SBI PMU extension and sscofpmf extension(ISA extension) allows to
implement most of the required features of perf. Remove the old
documentation which is not accurate anymore.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions