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| author |   Alexandre Ghiti <alexghiti@rivosinc.com> | 2023-06-06 15:04:44 +0200 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2023-06-07 07:13:53 -0700 |
| commit | 25abe0db92437fde463204c3e4eb5a71b62d6e5d (patch) | |
| tree | f68b8318d1220f37771d6994e28e2fd19f48902d /scripts/generate_rust_analyzer.py | |
| parent | riscv: mm: Ensure prot of VM_WRITE and VM_EXEC must be readable (diff) | |
| download | wireguard-linux-25abe0db92437fde463204c3e4eb5a71b62d6e5d.tar.xz wireguard-linux-25abe0db92437fde463204c3e4eb5a71b62d6e5d.zip | |
riscv: Fix kfence now that the linear mapping can be backed by PUD/P4D/PGD
RISC-V Kfence implementation used to rely on the fact the linear mapping
was backed by at most PMD hugepages, which is not true anymore since
commit 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear
mapping").
Instead of splitting PUD/P4D/PGD mappings afterwards, directly map the
kfence pool region using PTE mappings by allocating this region before
setup_vm_final().
Reported-by: syzbot+a74d57bddabbedd75135@syzkaller.appspotmail.com
Closes: https://syzkaller.appspot.com/bug?extid=a74d57bddabbedd75135
Fixes: 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear mapping")
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20230606130444.25090-1-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions