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| author |   Matt Roper <matthew.d.roper@intel.com> | 2022-08-23 13:24:49 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-08-26 08:49:35 -0700 |
| commit | 25bcc828d237cda65d34c736d70e4467fffb80b9 (patch) | |
| tree | 600e034af2208764617e59cc5c1396ce8e32d87b /scripts/generate_rust_analyzer.py | |
| parent | drm/i915/pxp: don't start pxp without mei_pxp bind (diff) | |
| download | wireguard-linux-25bcc828d237cda65d34c736d70e4467fffb80b9.tar.xz wireguard-linux-25bcc828d237cda65d34c736d70e4467fffb80b9.zip | |
drm/i915/dg2: Incorporate Wa_16014892111 into DRAW_WATERMARK tuning
Although register tuning settings are generally implemented via the
workaround infrastructure, it turns out that the DRAW_WATERMARK register
is not properly saved/restored by hardware around power events (i.e.,
RC6 entry) so updates to the value cannot be applied in the usual
manner. New workaround Wa_16014892111 informs us that any tuning
updates to this register must instead be applied via an INDIRECT_CTX
batch buffer. This will ensure that the necessary value is re-applied
when a context begins running, even if an RC6 entry had wiped the
register back to hardware defaults since the last context ran.
Fixes: 6dc85721df74 ("drm/i915/dg2: Add additional tuning settings")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6642
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220823202449.83727-1-matthew.d.roper@intel.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
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