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| author |   Michal Simek <michal.simek@amd.com> | 2024-11-27 17:01:22 +0100 |
|---|---|---|
| committer |   Alexandre Belloni <alexandre.belloni@bootlin.com> | 2025-01-13 00:41:24 +0100 |
| commit | 2a388ff22d2cbfc5cbd628ef085bdcd3b7dc64f5 (patch) | |
| tree | d05ea7aa2eb35707a43b42eb29f0a8e20e91306b /scripts/generate_rust_analyzer.py | |
| parent | rtc: loongson: clear TOY_MATCH0_REG in loongson_rtc_isr() (diff) | |
| download | wireguard-linux-2a388ff22d2cbfc5cbd628ef085bdcd3b7dc64f5.tar.xz wireguard-linux-2a388ff22d2cbfc5cbd628ef085bdcd3b7dc64f5.zip | |
rtc: zynqmp: Fix optional clock name property
Clock description in DT binding introduced by commit f69060c14431
("dt-bindings: rtc: zynqmp: Add clock information") is talking about "rtc"
clock name but driver is checking "rtc_clk" name instead.
Because clock is optional property likely in was never handled properly by
the driver.
Fixes: 07dcc6f9c762 ("rtc: zynqmp: Add calibration set and get support")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Cc: stable@kernel.org
Reviewed-by: Peter Korsgaard <peter@korsgaard.com>
Link: https://lore.kernel.org/r/cd5f0c9d01ec1f5a240e37a7e0d85b8dacb3a869.1732723280.git.michal.simek@amd.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions