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author | 2023-03-30 20:31:04 +0530 | |
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committer | 2023-04-14 09:58:14 +0300 | |
commit | 2efc8e1001acfdc143cf2d25a08a4974c322e2a8 (patch) | |
tree | 22c2460b42574abb701fa7062e508919ecce6de3 /scripts/generate_rust_analyzer.py | |
parent | drm/i915: disable sampler indirect state in bindless heap (diff) | |
download | wireguard-linux-2efc8e1001acfdc143cf2d25a08a4974c322e2a8.tar.xz wireguard-linux-2efc8e1001acfdc143cf2d25a08a4974c322e2a8.zip |
drm/i915/color: Fix typo for Plane CSC indexes
Replace _PLANE_INPUT_CSC_RY_GY_2_* with _PLANE_CSC_RY_GY_2_*
for Plane CSC
Fixes: 6eba56f64d5d ("drm/i915/pxp: black pixels on pxp disabled")
Cc: <stable@vger.kernel.org>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230330150104.2923519-1-chaitanya.kumar.borah@intel.com
(cherry picked from commit e39c76b2160bbd005587f978d29603ef790aefcd)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions