diff options
| author |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2024-12-19 18:55:36 -0500 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2024-12-20 14:17:56 -0500 |
| commit | 2f12e9c029315c1400059b2e7fdf53117c09c3a9 (patch) | |
| tree | 1ebcef521f260102e2294f0da4f0a40a27ad80e9 /scripts/generate_rust_analyzer.py | |
| parent | drm/xe/gsc: Make GSCCS disabling message less alarming (diff) | |
| download | wireguard-linux-2f12e9c029315c1400059b2e7fdf53117c09c3a9.tar.xz wireguard-linux-2f12e9c029315c1400059b2e7fdf53117c09c3a9.zip | |
drm/xe/dg1: Fix power gate sequence.
sub-pipe PG is not present on DG1. Setting these bits can disable
other power gates and cause GPU hangs on video playbacks.
VLK: 16314, 4304
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13381
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241219235536.454270-1-rodrigo.vivi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions