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| author |   Jacky Bai <ping.bai@nxp.com> | 2023-03-31 14:38:11 +0800 |
|---|---|---|
| committer |   Abel Vesa <abel.vesa@linaro.org> | 2023-04-09 17:12:49 +0300 |
| commit | 335aee51ffc72149ddf99755ba629f981f20e6b6 (patch) | |
| tree | 7333dac2839cff06b9a1275bf6b2d06954bdf7d2 /scripts/generate_rust_analyzer.py | |
| parent | clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parents (diff) | |
| download | wireguard-linux-335aee51ffc72149ddf99755ba629f981f20e6b6.tar.xz wireguard-linux-335aee51ffc72149ddf99755ba629f981f20e6b6.zip | |
clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate
If a divider's parent clock has fractional part, it will hard to round out a
more accurate clock rate for this divider, add the 'CLK_DIVIDER_ROUND_CLOSEST' flags
for such divider to get a more accurate clock rate.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230331063814.2462059-3-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions