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| author |   Sia Jee Heng <jeeheng.sia@starfivetech.com> | 2024-05-02 00:37:51 -0700 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2024-07-24 07:33:37 -0700 |
| commit | 38738947db38520b58b7dae64bd0eec513e83139 (patch) | |
| tree | 63bdb4df274f61fa072c481a5ea80ff97bb29a72 /scripts/generate_rust_analyzer.py | |
| parent | Linux 6.10-rc1 (diff) | |
| download | wireguard-linux-38738947db38520b58b7dae64bd0eec513e83139.tar.xz wireguard-linux-38738947db38520b58b7dae64bd0eec513e83139.zip | |
RISC-V: ACPI: Enable SPCR table for console output on RISC-V
The ACPI SPCR code has been used to enable console output for ARM64 and
X86. The same code can be reused for RISC-V. Furthermore, SPCR table is
mandated for headless system as outlined in the RISC-V BRS
Specification, chapter 6.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Link: https://lore.kernel.org/r/20240502073751.102093-2-jeeheng.sia@starfivetech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions