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| author |   Christian König <christian.koenig@amd.com> | 2022-09-19 14:00:33 +0200 |
|---|---|---|
| committer | Christian König <christian.koenig@amd.com> | 2022-09-19 20:45:17 +0200 |
| commit | 3cc3dd73c420dc70cd366f91a680035ef47edf4f (patch) | |
| tree | 15613c12c8a5b9565f5a7196c7bbd6246cca8fe8 /scripts/generate_rust_analyzer.py | |
| parent | Revert "drm/bridge: chrontel-ch7033: Add byteswap order setting" (diff) | |
| download | wireguard-linux-3cc3dd73c420dc70cd366f91a680035ef47edf4f.tar.xz wireguard-linux-3cc3dd73c420dc70cd366f91a680035ef47edf4f.zip | |
dma-buf: fix dma_fence_default_wait() signaling check
That check must now come after grabing the spinlock, not before.
Signed-off-by: Christian König <christian.koenig@amd.com>
Fixes: b96fb1e724ae ("dma-buf: dma_fence_wait must enable signaling")
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220919120618.113332-1-christian.koenig@amd.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions