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| author |   Lucas Stach <l.stach@pengutronix.de> | 2024-10-25 17:14:46 +0200 |
|---|---|---|
| committer | Lucas Stach <l.stach@pengutronix.de> | 2024-10-28 16:49:09 +0100 |
| commit | 4f8dbadef085ab447a01a8d4806a3f629fea05ed (patch) | |
| tree | 6bba5e6beab056c5dc4608db975cae0900c89902 /scripts/generate_rust_analyzer.py | |
| parent | drm/etnaviv: always allocate 4K for kernel ringbuffers (diff) | |
| download | wireguard-linux-4f8dbadef085ab447a01a8d4806a3f629fea05ed.tar.xz wireguard-linux-4f8dbadef085ab447a01a8d4806a3f629fea05ed.zip | |
drm/etnaviv: flush shader L1 cache after user commandstream
The shader L1 cache is a writeback cache for shader loads/stores
and thus must be flushed before any BOs backing the shader buffers
are potentially freed.
Cc: stable@vger.kernel.org
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions