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| author |   Xingyu Wu <xingyu.wu@starfivetech.com> | 2024-08-26 16:04:29 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2024-08-29 12:24:42 -0700 |
| commit | 538d5477b25289ac5d46ca37b9e5b4d685cbe019 (patch) | |
| tree | d709583911c34da618bca8ab76ffb62622699b25 /scripts/generate_rust_analyzer.py | |
| parent | clk: qcom: gcc-sm8650: Don't use shared clk_ops for QUPs (diff) | |
| download | wireguard-linux-538d5477b25289ac5d46ca37b9e5b4d685cbe019.tar.xz wireguard-linux-538d5477b25289ac5d46ca37b9e5b4d685cbe019.zip | |
clk: starfive: jh7110-sys: Add notifier for PLL0 clock
Add notifier function for PLL0 clock. In the function, the cpu_root clock
should be operated by saving its current parent and setting a new safe
parent (osc clock) before setting the PLL0 clock rate. After setting PLL0
rate, it should be switched back to the original parent clock.
Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Cc: stable@vger.kernel.org
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Link: https://lore.kernel.org/r/20240826080430.179788-2-xingyu.wu@starfivetech.com
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Tested-by: Michael Jeanson <mjeanson@efficios.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions