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authorThomas Gleixner <tglx@linutronix.de>2022-05-27 10:32:08 +0200
committerThomas Gleixner <tglx@linutronix.de>2022-05-27 10:32:08 +0200
commit57963a92a70b037aa22544fbc34742e5be689c04 (patch)
treeea4591ebe6bdd6dea8286c4eef6cc7906716acb3 /scripts/generate_rust_analyzer.py
parenttimers: Provide a better debugobjects hint for delayed works (diff)
parentclocksource/drivers/oxnas-rps: Fix irq_of_parse_and_map() return value (diff)
downloadwireguard-linux-57963a92a70b037aa22544fbc34742e5be689c04.tar.xz
wireguard-linux-57963a92a70b037aa22544fbc34742e5be689c04.zip
Merge tag 'timers-v5.19-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core
Pull clockevent/clocksource driver updates from Daniel Lezcano: - Add Mediatek MT8186 DT bindings (Allen-KH Cheng) - Remove dead code corresponding of the IXP4xx board removal (Linus Walleij) - Add CLOCK_EVT_FEAT_C3STOP flag for the RISC-V SBI timer (Samuel Holland) - Do not return an error if there are multiple definitions of the sp804 timers in the DT (Andre Przywara) - Add the missing SPDX identifier (Thomas Gleixner) - Remove an unncessary NULL check as it is done right before at probe time for the timer-ti-dm (Dan Carpenter) - Fix the irq_of_parse_and_map() return code check on onexas-nps (Krzysztof Kozlowski) Link: https://lore.kernel.org/lkml/b5a83e54-1ee1-f910-4be4-bc3bf1015243@linaro.org
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